Blockram: RAM model read/write

At least, these signals seem to have wrong polarity:

vram_we_sig <= Wr_n;
vram_re_sig <= Rd_n;

The other other point is, that the timing may be inappropriate for your design, but that can't be seen from the shown code. FPGA internal RAM act as synchronous RAM, you should check the timing to see if read and write operation occur at the intended moment. Also registered or non-registered read operation can be choosen.

I wonder, why conditional assignment (a multiplexer) is used for the RAM input signals, but it shouldn't have any effect.