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At least, these signals seem to have wrong polarity:
vram_we_sig <= Wr_n;
vram_re_sig <= Rd_n;
The other other point is, that the timing may be inappropriate for your design, but that can't be seen from the shown code. FPGA internal RAM act as synchronous RAM, you should check the timing to see if read and write operation occur at the intended moment. Also registered or non-registered read operation can be choosen.
I wonder, why conditional assignment (a multiplexer) is used for the RAM input signals, but it shouldn't have any effect.
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Thanks for replying.
The timing may be wrong... I will try to check this.
However, the polarity in the said signals are ok. they are asserted LOW:
vram_we_sig <= Wr_n
vram_re_sig <= Rd_n
Wr_n is the Z80 write enable signal.
vram_we_sig is the RAM write enable signal.
The multiplexers are there because it will address differente RAM/ROMS, and this is only some code to debug the block ram access.
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