Blockram: RAM model read/write

These seems to have worked very well:

	-- Write into RAM
	vram_wraddress_sig <= A - x"2000";
	vram_wren_sig <= not Wr_n when (A >= x"2000" and A <= x"4000");
	vram_data_sig <= DO_CPU;
	-- Read from RAM
	vram_rden_sig <= Rd_n;
	vram_rdaddress_sig <= A - x"2000";
        DI_CPU <= vram_q_sig when (A >= x"2000" and A <= x"4000") else
		         D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
                         .....

Also, I am now able to write using a 3.58Mhz clock, and read at 25Mhz.

However, I am very confused. The LPM model for ram have control signals asserted low:

ENTITY vram8k IS

PORT

(

data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);

rdclock : IN STD_LOGIC ;

rden : IN STD_LOGIC := '1';

wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);

wrclock : IN STD_LOGIC ;

wren : IN STD_LOGIC := '1';

q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END vram8k;

In my code, asserting write HIGH will write data. Asserting READ LOW will read data. something is very wrong here.... Is it me?