Blockram: RAM model read/write

Little explanation:

It is a SoC based on Z80.

When Z80 writes to RAM, it must be above 0x2000h.

When it reads, it can be ROM (0x0000h to 0x1FFFh), or RAM (above 0x2000h).

In the simulation (only the RAM model, not the full SoC), the read operations returned the data only on the 3rd clock cycle.

But, starting over, this is the code I understand you guys suggested:

	-- Write into RAM
	vram_wraddress_sig <= A - x"2000";
	vram_wren_sig <= (not Wr_n) or (not MReq_n) when A >= x"2000";
	vram_data_sig <= DO_CPU when Wr_n = '0' and MReq_n = '0' and A >= x"2000";
	-- Read from RAM
	vram_rden_sig <= '1';
	vram_rdaddress_sig <= A - x"2000";
	DI_CPU <= vram_q_sig when (Rd_n = '0' and MReq_n = '0' and A >= x"2000") else
			D_ROM when (Rd_n = '0' and MReq_n = '0');
This is the RAM instantiation:
	vram8k_inst : work.vram8k PORT MAP (
		data	 	=> vram_data_sig,
		rdaddress	=> vram_rdaddress_sig(12 downto 0),
		rdclock	 	=> Clk_Z80,
		rden	 	=> vram_rden_sig,
		wraddress	=> vram_wraddress_sig(12 downto 0),
		wrclock		=> Clk_Z80,
		wren	 	=> vram_wren_sig,
		q	 	=> vram_q_sig
	);

The write operations are OK?

What may I change to read correctly from RAM? (above 0x2000h in Z80, which is 0x0000 in RAM) ?

Thanks again.