Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorBlockram: RAM model read/write
Hello, Can someone point me out how I can read/write to the following blockram RAM model ? I can read and write to external SRAM, but I am not able to make this work using blockram. Could...
Altera_ForumHonored Contributor
Honored ContributorDisplaying the RAM timing in simulator or using SignalTap should help to understand what's wrong.
If Wr_n is active for one clock cycle only, vram_data_sig assignment in edge sensitive process code causes the data to be one cycle late. Write data must be present simultaneously with address and WE signal. If any multiplex action is needed, it should be placed in concurrent code or outside of the edge sensitive condition.
