Forum Discussion
Altera_Forum
Honored Contributor
17 years agoThanks everyone for the tips.
But I really will need some definitive help on this. I am trying this for a few days now, but have not achieved knowledge enough to make this work. Here is the latest code.
-- Write into RAM
vram_wraddress_sig <= A - x"2000";
vram_wren_sig <= (not Wr_n) or (not MReq_n);
process (Clk_Z80)
begin
if Clk_Z80'event and Clk_Z80 ='1' then
if Wr_n = '0' and MReq_n = '0' and A >= x"2000" then
vram_data_sig <= DO_CPU;
elsif Rd_n = '0' and MReq_n = '0' and A >= x"2000" then
vram_q_sig_reg <= vram_q_sig;
end if;
end if;
end process;
-- Read from RAM
vram_rden_sig <= '1';
vram_rdaddress_sig <= A - x"2000";
DI_CPU <= vram_q_sig_reg when (Wr_n = '0' and MReq_n = '0' and A >= x"2000") else
D_ROM when (Rd_n = '0' and MReq_n = '0');
--
vram8k_inst : work.vram8k PORT MAP (
data => vram_data_sig,
rdaddress => vram_rdaddress_sig(12 downto 0),
rdclock => Clk_Z80,
rden => vram_rden_sig,
wraddress => vram_wraddress_sig(12 downto 0),
wrclock => Clk_Z80,
wren => vram_wren_sig,
q => vram_q_sig
);
It is a simple operation: Write into RAM, Read from RAM.