Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

blinking of two LED's.

Hello,

Hi guys. i wrote a program in verilog of updown counter.

As the board I am using is of 50 Mhz, so to actually see the LED blinking I divided the clock.

My output was routed to single LED but when i downloaded my code two LED's started blinking whereas i just

routed my output to one LED.

I am in a mess.

Can anybody help me with this?

Hope to hear from you soon guyz.

Regards

Muzammil Iqbal

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Since the board layout is totally unknown with what you have explained, it could be that the leds are connected to each other and therefore are both blinking.

    If that isn' t the problem, than maybe you should post a board layout, or the name of the board. Maybe even the code can help
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Since the board layout is totally unknown with what you have explained, it could be that the leds are connected to each other and therefore are both blinking.

    If that isn' t the problem, than maybe you should post a board layout, or the name of the board. Maybe even the code can help

    --- Quote End ---

    the board i am using is nios development board stratix edition containing startix EP1S40F780C5. The layout of the board is not available online, i tried many times searching for that, even posted a requested in altera forums but nobody replied.

    It will be great if you can help me out. I am also providing the source code.

    Hope to hear from you soon.

    module UpDown(clk, clk_s, clk_s1, count);

    input clk;

    wire reset;

    wire enable;

    output reg[25:0]count;

    output reg clk_s;

    output reg clk_s1;

    assign reset =0;

    assign enable=1;

    always @ (posedge clk)

    begin

    // If reset is 1

    if (reset == 1'b1)

    begin

    count <= 26'h0000000;

    clk_s <= 0;

    clk_s1 <=0;

    end

    // If counter is enabled

    else if (enable == 1'b1)

    begin

    count <= count + 1'b1;

    if (count == 26'h2faf080)

    begin

    count <= 26'h0000000;

    clk_s <= ~clk_s;

    clk_s1<= ~clk_s1;

    end

    end

    end

    endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Are you sure about the polarity of the reset signal? Is it coming from an FPGA pin? It could be an active low signal.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I don't know Verilog, but in your code you get 2 outputs, don't you ?

    Even if ONE is connected to ONE LED as you expect,

    the other output is connected to another LED as Quartus is free to decide.

    Look at warning messages, and pin planner.

    Maybe I am wrong.

    Regards.