Bit extending when adding

I thought about this long and hard, and I respectfully disagree.

When dealing with digital computers, everything is a wire or a transistor but to design using only those two things is absurd.

Since unsigned and signed are subtypes of std_logic_vector, a simple cast is all that is required to interface to std_logic_vector. I believe the ambiguity of the number being represented far outweighs a few casts.

If you were to design a double precision floating point arithmetic module, would you interface to a 64-bit std_logic_vector, or would you create a record for sign, exponent and fraction?

In cases where the number could be either signed or unsigned, std_logic_arith should still not be used since you want to convey what type it is being interpreted as back to the person reading the code.

The purpose is to capture the original intent of the design. VHDL allows the designer to keep the original intent intact with very little impact on the rest of the code.

Unless you're coding for job security, I think signed and unsigned types should be used to convey intent by the designer, but I respect your opinion that they are not required in most cases.