Binary Divider

If you are just wanting to try out the Altera tool, then you can just instantiate the lpm_divide module in your test HDL and run it through Quartus II's synthesis and place&route. Or, you can write your own HDL code to implement a binary divider if you want (but for the purpose of taking Quartus for a test drive, I think it doesn't matter).

Quartus->File menu has a New Project wizard that takes you through the steps of creating a new Quartus project (just define where your HDL is, what FPGA are you targeting, etc)

There is a button on Quartus that looks like the "play" button on a DVD player; clicking on that runs the design through all the necessary tools, pretty simple.

Found some arithmetic design examples in the following link. You may also want to try it out.

http://www.altera.com/support/examples/exm-arithmetic.html

Do you want a pipelined divider (result every clock cycle after an initial latency) or a serial divider (low throughput)?

Pipelined dividers are big due to the nature of division whereas serial dividers are fairly tiny (approximately 2.5 LEs per bit roughly). A serial divider performs division by using long division which is why it's so small (because the operation is just shift, compare, and subtract). You can also make hybrid serial + parallel dividers where multiple bits are operated on each clock cycle.

If you can't find anything leave me a message and I'll see if I can find one of mine.

I would say have a look at these books as a starting point

Computer Organisation & Design - Patterson and Hennessey

Digital Arithmetic - Ercegovac and Lang

Computer Arithmetic Algoithms - Isreal Koren

and to a lesser degree this one

Elementary Functions: Algorithms and Implementation - Muller

Trying to implement any mathematical algorithm in hardware might be heavy going to begin but the end result can be very lucrative ;)