Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI was originally planning to use it as both a frame buffer and for the Nios core running ethernet.
I'm unsure of how much i can get away with. I imagine i'll need to keep it 32 bits wide. socrates, your working on something similar? how much ram are you using? I require to get it off the development boards so as to achgeive the required complexity, plus its something i want to do if its possible. 2 fpgas In regards to this, as it is now on my De2, i have the camera feeding pixels at 50Mhz. This would mean that the IO is fast enough to handle that. So is it possible that i connect two fpgas using a avalon ST bus style connection. (32 data pins + 5 or so control signals) Having just the ethernet, and SDRAM on one FPGA and the other has the auxiliaries. This could mean that i use 2 160 pin FPGAs (15K LEs each). Am i crazy?