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Honored Contributor
Honored ContributorBest place for termination resistor
I am connecting a Micrel Gig-E PHY to a Cyclone III FPGA. Most of it is fairly straightforward - and I've got all GMII interface routed cleanly. The only trick is the TXCLK/GTXCLK pin. It's a s...
Altera_ForumHonored Contributor
Honored ContributorI hadn't considered it, but the GTX clock out is on a local clock pin (DPCLK0), so theoretically it could be used as an input when in MII mode. It was a somewhat serendipitous route, as I didn't intentionally route the net there (I was trying to avoid vref pins, though)
If you configure those pins as bidirs, can you still route an input on the pin to the local clock net? I had routed the signal to a normal I/O pin, and a dedicated clock-input pin, since I figured the MAC core clock would be a high fan-out net that would probably cross quadrants. At worst, I could try it. The wire is already there, but it really should hurt anything to have the dedicated clock-in pin "listening" - since it will be high-impedance.
