Benchmark - how to raise clock frequency?

Thank you for the answer.

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This 215MHz value looks quite optimistic. According to Altera's document it was measured on a EP3C40F324C6. I guess you have a C7 or C8 on your board, that will be a bit slower.

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You're right, i've got the C8 speed grade. The "Cyclone III Device Handbook, Vol2, page 25" shows differences in speed only around 20% between C6 and C8. So the speed grade is one reason, but cannot be the only one, from my point of view.

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Do you have timing violations when you recompile your design with a higher frequency?

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Sorry, i didn't get that... Which timing violations do you mean? I don't have errors when compiling, but when i try to run the benchmark with the NIOS II IDE (Eclipse), either the download verify fails or the processor does not respond, if the PLL frequency is configured too high.

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You can try and add some pipelines, it will help increase the fmax. As an example a Avalon MM pipeline bridge between the CPU instruction and data masters and the JTAG debug module usually helps.

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Hm, I added this pipeline bridge, but I can't see much difference now. The clock frequency is stucked at around 130MHz for eco, ~80MHz for the standard and ~100MHz for the fast NIOS.