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Honored Contributor
Honored ContributorBehaviour pins powered down stratix 3 FPGA
What is the behaviour of the io's of an unpowerd fpga device? Undefined, tristated, short circuit...? I have two S3 devices connected with a fast lvds link. In standby mode the link is unused a...
Altera_ForumHonored Contributor
Honored ContributorThe topic is discussed in detail in the Stratix III Handbook under hot socketing
Generally, you have to assure, that Stratix maximum input voltage ratings aren't exceeded, also if the on-chip termination isn't active during power-up. There should be no problem with LVDS channels. Care should be taken with inputs, that need e.g. PCI clamp diodes to keep the voltage limits.
