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Altera_Forum
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16 years ago

Behaviour pins powered down stratix 3 FPGA

What is the behaviour of the io's of an unpowerd fpga device? Undefined, tristated, short circuit...? I have two S3 devices connected with a fast lvds link. In standby mode the link is unused a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The topic is discussed in detail in the Stratix III Handbook under hot socketing

Generally, you have to assure, that Stratix maximum input voltage ratings aren't exceeded, also if the on-chip termination isn't active during power-up. There should be no problem with LVDS channels. Care should be taken with inputs, that need e.g. PCI clamp diodes to keep the voltage limits.