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Altera_Forum's avatar
Altera_Forum
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18 years ago

Beginners problems. i need assistance...

Before you read this: it may look like i am ranting and raving. That is not the case.

I am just frustrated after a week of problems, that's all.

All the questions i have are very simple basic questions. Things that take 1 click or 1 line of code in the IDE and C compilers from Keil or Tasking, yet turn out to be a complete nightmare in this NIOS IDE if you are starting with this tool coming from a diffrent environment ( 8051 C compiler from Keil )

I am sure that they are very easy for someone who knows this development environment. But for a starting idiot like me this is a friggin nightmare.

For the past week i have been trying to get support from Altera on my questions.

The mysupport is no good. I have now 6 open cases. None of them have been answered to my satisfaction. I have been playing ping-pong with them and ave only gotten half answers. I want to move forward.

I have serious 'beginners' problems with the nios development tools.

a simple example:

Make a new C/C++ project.

Add a file called main_program.c with the following code : void main(void) {}

Click build. The builder crashes with some cryptic error. Now what ?

Other questions i have that go unanswered :

- How do i assign a variable to a specific address. ( like the _at_ directive in Keil's C51 )

- How do i write an interrupt handler ? ( in the 8051 world this is easy just write 'interrupt x) after your function header and you are done. the linkers know what to do)

- What is the layout in memory of a progam ? I need to know exactly how a program is stored in RAM and how to put a binary file there. All the solutions given are only half solutions that either don't work or are plain wrong. Solutions like 'you need to make an SREC file' are not solutions. I need to see a step by step example. I don't know these command line tools. It took me a while to find out that this is a motorola S record and i need to use some tool called nios2-elf-objcopy to generate one. I played with the nios2-elf-objcopy a bit but can't get it to work. First it crashed because it couldnt find some DLL ( cygwin-whatever) after finding that and putting it in the same directory it still crashes.

I want a step by step example. Besides, i don't want a motorola format. i need a simple binary file or intel hex file i can load into ram. ( i have access to the nios main SRAM through an avalon master. So i can read 4 bytes from the binary file at a time and store them as 32 bit words. When all is done i bring the nios out of reset and the program should begin executing. ( hopefully ... )

I want to know what the layout of the file is. If i read the first four bytes in the binary file

these should go to the first 32 bit word ( my SRAM is 32 bit wide ) What is the byte layout ?

suppose the file looks like this

0xaa

0xbb

0xcc

0xdd

do i store DDCCBBAA into the first 32 bit word or do is store AABBCCDD into the first 32 bit word ?

On the demo program : I don't need an operating system , i dont need the jtag debugger, i dont need 'printf' ( why is the printf demo 70 kilobyte when compiled ? it should be 25 bytes ... 12 to store the string 'hello world' and a couple of instructions to send them one by one to the uart and wait for the transmit flag to clear. anyway , back tot he point)

i need nothing. The demo program i need is 20 lines of C code ( if i have such a demo i can adapt and extend it to handle the real job i want to run on the nios. i don't expect anyone to write my whole system. I have the system running on an 8051 but want to port to nios so i can do 32 bit arithmetic faster.

All i need is a simple skeleton. I can take it from there.

The program needs to react to 2 hardware interrupts, read data from some memory locations, do some simple calculations ( integer math ) perform a simple decision and write some output to some other memory locations. The compiled machine language program is maybe 30 instructions.

here is the program in pseudo code :

int a _at_ 0x00100000; // in the DPRAM

int b _at_ 0x00100004; // in the DPRAM

int c _at_ 0x00100008; // in the DPRAM

int d _at_ 0x001F0008; // a hardware IO port ( register )

int e _at_ 0x001F0000; // a hardware IO port ( combinatorial block)

void int_1_handler(void) handles interrupt 1

{

c = ((b+1) << 4) +a;

e=1;

}

void int_2_handler(void) handles interrupt 2

{

if c > 0 : c = c -1;

e=1;

}

void main (void)

{ while 1

{

if (d == 1) d = 0 else d =1;

}

}

I have the nio shardwar ealready defined in SOPc builder and it synthesizes

The nios has SRAM from 0000000 to 001FFFFF That is where the program ,stack and all other stuff needs to resides.

0x001F00008 is a hardware io port. ( there is a peripheral mapped there )

Locations 0x001000000 and the others reside in an on board dual port ram. an external system loads data into A and B and triggers either interrupt 1 or 2.

0x001F00008 is also a hardware port. (a custom peripheral. there is no 'memory' there. no flipflops are there, only an address decoder and some combinatorial logic. if a write is detected to bit 0 if that address a block of hardware is triggered that reads memory location 8 in the dual port ram to retrieve the data belonging to variable 'c'.

After posting on various forums someone explained that i can use a define construction like :

# define a (*(volatile unsigned int *) (0x00100000))

# define b (*(volatile unsigned int *) (0x00100004))

etcetera. is this correct ? Will the linker know it needs to stay away form those locations ? Will it know that it can not use those specific addresses to store anything ?

What if i map variables in the main memory ( the main SRAM ) lets say i map something like this :

# define global_q (*(volatile unsigned int *) (0x00004000))

this falls in the middle of the SRAM. will the linker know that this is no-go area and map both program and data around this specific location ?

i have a bunch of variables that need to reside at very specific locations in SRAM because they get written through an avalon master port that can stop the NIOS, change the contents of those locations and let the NIOS resume. For some other storage is use dual port ram so i don't need to stop the nios. ( the nios will be busy in another memory region at that time. that is guaranteed by the way my hardware is built. ) DMA is not an option. i wan ttht nios to do one thing while i load a part of its memory with information for the next thing.

More questions :

How can i see the compiled output as machine language ( ASM opcodes ) (The Keil compiler can show you every single line of 'c' code and the machine language created for it. I would like to see what the compiler does with the code i write.)

Is there ANYONE available who can spend half a day sitting next to me and guide me step by step on how to create a blank project with only an empty main routine and 2 interrupt handlers. I really need to 'see' how it is done.

A big thanks upfront for the brave soul who want to help me. Oh, and it doesn't need to be for free. I am located in San Jose.

desperate ...

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I think you will benefit greatly by adding 2 appnotes to your reading list. The first is recently released and marked with a red "New" flag, titled "AN 459: Guidelines for Developing a Nios II HAL Device Driver", listed in the "Software Development" section of the Nios II Literature page. It provides an example for HAL Memory Mapped I/O. (Nice 2001 - A Space Odyssey reference by the way. I hadn't heard that one yet :cool:

    See also for a skeleton which shows installation of a timer interrupt handler in fast on-chip memory an appnote titled "Using Nios II Tightly-Coupled Memory Tutorial", listed in the "Hardware and System Development" section. (This is the same one Rick mentions in point number 3 below). Both documents come with example software files to download as well. Grab the "Design file" and "bit_bang_uart.c file" links below each of the docs. Both are available on the Nios II Literature page, at:

    http://www.altera.com/literature/lit-nio2.jsp

    You will soon learn about the true beauty of the soft-cores in FPGA solution, where you could decide to throw down 60 Nios processors into one FPGA (granted, a larger sized variety of FPGA), each one dedicated to handling a single interrupt, all running truly in parallel in hardware.

    I think you will like the performance boost afforded by our exception handling custom instruction as well (also mentioned by Rick). This essentially extends the Nios II architecture instruction set with any command you would like to perform entirely in hardware. You can also write your own custom instructions, but we wrote the one to speed up the exception handling funnel for you.

    Additionally, be sure to always include the System ID component in your hardware design. This will save you hours of frustration chasing a problem if you accidentally load a syslib which does not match the currently loaded SOPC Builder design, by catching it and warning you during the attempt to download.

    Best of luck, and welcome to the world of soft-core microprocessors!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    spooky ....

    int x =0;

    int main(void)

    {

    x = x+1;

    }

    Needs 6482 bytes of code with optimize set to 3 ( smallest footprint )

    Any leads on how to tune the compiler more ?

    I had a long discussion today with some 'experts'.

    The outcome is : NIOS in the trashcan.

    This thing is completely un-usable as a processor core. Maybe if you want to start 'accelerating' functions and use all the advanced stuff. but as a generic core ? useless.

    Right now i stuffed an 8051 IP core in the FPGA. 1400 Le's. It's ticking away happily at 48 MHz ( its a single clock core. only MUL and DIV take 4 ticks and JMP takes 2 ticks ) i can blast it with interrupts at over 1 MHz.. and its still sleeping 40 % of its time... try doing that with a nios at 48 MHz...

    Somebody needs to wake up at altera and fix this processor (and the toolchain for that matter) ...

    SOPC builder 7.2 has a serious bug !

    if you instantiate an avalon master and click 'generate', the master port is not brought to the outside world. you can not connect to it ! I have a bunch of things that connect to an avalon master port... whoops .... there goes the design. ( DPRAM sits in SOPC builder. the second port comes out through an avalon master port. )
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    spooky ....

    int x =0;

    int main(void)

    {

    x = x+1;

    }

    --- Quote End ---

    I got 156 bytes following the hello_world_small example.

    --- Quote Start ---

    SOPC builder 7.2 has a serious bug !

    if you instantiate an avalon master and click 'generate', the master port is not brought to the outside world. you can not connect to it ! I have a bunch of things that connect to an avalon master port... whoops .... there goes the design. ( DPRAM sits in SOPC builder. the second port comes out through an avalon master port. )

    --- Quote End ---

    Are you exporting the signals that you want to see at the top-level of your SoPC Builder design?

    =====

    Many people find SoPC Builder and Nios II highly useful. Wart and "foible" free: No. Useful: Yes.

    You might be correct that it won't suit your needs for this particular application, but to write it off completely is being short-sighted, at best.

    From what I know (very little) of your application, I'd advise you to:

    1. Follow the hello_world_small example for code size reduction.

    - Alternately, you could look at the hello_alt_main or hello_led examples, which circumvent the HAL layer entirely, though I wouldn't advise doing it until you really know your way around a Nios II based system.

    2. Utilize the Interrupt Vector custom instruction.

    3. Look at re-designing your hardware to better suit the way in which Nios II/Avalon function.

    Good luck!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    thanks

    1) that seems to work better.

    2) done that. its still too slow....

    3) can't change an ASIC ... i am using the FPGA to emulate the ASIC. the ASIC design is done the way it's done. I have no control over it ( for very specific reasons ... )