Honored Contributor
Honored ContributorI think you will benefit greatly by adding 2 appnotes to your reading list. The first is recently released and marked with a red "New" flag, titled "AN 459: Guidelines for Developing a Nios II HAL Device Driver", listed in the "Software Development" section of the Nios II Literature page. It provides an example for HAL Memory Mapped I/O. (Nice 2001 - A Space Odyssey reference by the way. I hadn't heard that one yet :cool:
See also for a skeleton which shows installation of a timer interrupt handler in fast on-chip memory an appnote titled "Using Nios II Tightly-Coupled Memory Tutorial", listed in the "Hardware and System Development" section. (This is the same one Rick mentions in point number 3 below). Both documents come with example software files to download as well. Grab the "Design file" and "bit_bang_uart.c file" links below each of the docs. Both are available on the Nios II Literature page, at: http://www.altera.com/literature/lit-nio2.jsp You will soon learn about the true beauty of the soft-cores in FPGA solution, where you could decide to throw down 60 Nios processors into one FPGA (granted, a larger sized variety of FPGA), each one dedicated to handling a single interrupt, all running truly in parallel in hardware. I think you will like the performance boost afforded by our exception handling custom instruction as well (also mentioned by Rick). This essentially extends the Nios II architecture instruction set with any command you would like to perform entirely in hardware. You can also write your own custom instructions, but we wrote the one to speed up the exception handling funnel for you. Additionally, be sure to always include the System ID component in your hardware design. This will save you hours of frustration chasing a problem if you accidentally load a syslib which does not match the currently loaded SOPC Builder design, by catching it and warning you during the attempt to download. Best of luck, and welcome to the world of soft-core microprocessors!
