Honored Contributor
Honored Contributorspooky ....
int x =0; int main(void) { x = x+1; } Needs 6482 bytes of code with optimize set to 3 ( smallest footprint ) Any leads on how to tune the compiler more ? I had a long discussion today with some 'experts'. The outcome is : NIOS in the trashcan. This thing is completely un-usable as a processor core. Maybe if you want to start 'accelerating' functions and use all the advanced stuff. but as a generic core ? useless. Right now i stuffed an 8051 IP core in the FPGA. 1400 Le's. It's ticking away happily at 48 MHz ( its a single clock core. only MUL and DIV take 4 ticks and JMP takes 2 ticks ) i can blast it with interrupts at over 1 MHz.. and its still sleeping 40 % of its time... try doing that with a nios at 48 MHz... Somebody needs to wake up at altera and fix this processor (and the toolchain for that matter) ... SOPC builder 7.2 has a serious bug ! if you instantiate an avalon master and click 'generate', the master port is not brought to the outside world. you can not connect to it ! I have a bunch of things that connect to an avalon master port... whoops .... there goes the design. ( DPRAM sits in SOPC builder. the second port comes out through an avalon master port. )
