Beginner questions on HDL component mapping

Thank you very much FvM. I'm a little more confused to be honest. So the code I am examining has something like this:

 
ARCHITECTURE arch of ent IS
....
signal someSignal1: STD_LOGIC;
signal someSignal2: STD_LOGIC
....
BEGIN
component1: ENTITY work.LED_FLASHER
PORT MAP (
LEDCLK = someSignal1;
LED=> led_number1 );
...
...
component2: ENTITY work.LED_FLASHER
PORT MAP (
LEDCLK => someSignal2,
LED => led_number2 );
...
END ARCHITECTURE arch

So I have tewdifferent signals mapping to LED_FLASHER, LEDCLK and LED. First is an input and the second is an output. Basically one output 'LED' is used to drive two led's (led_number1 and led_number2). Think of someSignals as two different clocks. And the LED's are flashed according to these clocks.

So when someSignals are mapped concurrently, how would this operate? Why wouldn't this create a multiple driver error?

Some explanation or a reference is very much appreciated.

Cheers.