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Basically, for clocks, you wouldnt
Allowing multiple drivers allows you to model tri-state buffers. These do not exist internally on a FPGA, but do exist on output pins.
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Thank you very much Tricky. You just explained a "multiple driver" error I have been getting and had no idea what I was doing. Thank you for that.
I am still a little confused about multiple mapping. Could you tell me what would happen if I do this multiple mapping the other way. For example,
ARCHITECTURE arch of ent IS
....
signal CLK: STD_LOGIC;
....
BEGIN
component1: ENTITY work.LED_FLASHER
PORT MAP (
LEDCLK => CLK );
...
...
component2: ENTITY work.LED_FLASHER
PORT MAP (
LEDCLK => CLK );
...
END ARCHITECTURE arch
What would happen in this case if I do multiple mappings to a component port?
Thank you very much for all the input.
Cheers.
Honored Contributor
