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Thank you FvM.
Sorry I have made a mistake. The code considers a signal, CLK, being mapped to outputs of two components. I am confused as to what happens in this cae and why would you use such multiple mapping.
Thank you.
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Basically, for clocks, you wouldnt
Allowing multiple drivers allows you to model tri-state buffers. These do not exist internally on a FPGA, but do exist on output pins.
For example if you did this:
sig <= '1';
sig <= '0';
In simulation you would see 'X' (Unknown) and the synthesisor would give you an error talking about multiple drivers on "sig"
Whereas if you did this:
sig <= 'Z';
sig <= '1';
in simulation sig would be '1' and systhesis would be fine.
Tri state buffers are used on inout ports. The inout port type should only be used at the top level. example below:
port (
data_port : inout std_logic_vector
);
......
--tri-state buffer
dat_port <= (others => 'Z') when read_en = '1' else output_data;
--input register
process(clk)
begin
if rising_edge(clk) then
if read_en = '1' then
input_data <= data_port;
end if;
end if;
end process;
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