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Altera_Forum
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11 years ago

Beginner device CPLD/FPGA selection for anti-aliasing filter

Hi all, I am working on a HW design for power analysis of 8channel 50/60Hz signals that are sampled @ around 50kHz / channel. These signals needs to be filtered after sampling before transforma...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Maybe this thread is moving off-topic, but can someone explain to me why an ADC (PCM1808) with 24-bit resolution have a gain error of typ3% max6%?

Of course this could probably be fixed in design with calibration, but it seems a bit high with respect to the number of bits.

I also do not find any information regarding gain accuracy vs temperature in the datasheet :-/

http://www.ti.com/lit/gpn/pcm1808