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Altera_Forum
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11 years ago

Beginner device CPLD/FPGA selection for anti-aliasing filter

Hi all, I am working on a HW design for power analysis of 8channel 50/60Hz signals that are sampled @ around 50kHz / channel. These signals needs to be filtered after sampling before transforma...
Altera_Forum's avatar
Altera_Forum
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11 years ago

CIC usage would primarly reduce complexity, that's why it's classically used for multi-rate filters of oversampling ADCs. But I agree that a serial FIR won't consume much resources besides block RAM. In so far it's a straightforward solution, even with quite large number of coefficients if you can afford the RAM capacity.

The WM8731 codec untilized on many Terasic boards can be used with 8 kHz standard sampling rate, or any rate of your choice by adapting the clock frequency.