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Altera_Forum
Honored Contributor
Honored ContributorBeginner device CPLD/FPGA selection for anti-aliasing filter
Hi all, I am working on a HW design for power analysis of 8channel 50/60Hz signals that are sampled @ around 50kHz / channel. These signals needs to be filtered after sampling before transforma...
Altera_ForumHonored Contributor
Honored ContributorAn economic implementation would e.g. use a 4:1 CIC decimator and a higher order FIR filter for the last decimation stage. In any case, there's a tradeoff between filter transition steepness and required filter complexity.
Did you notice that audio ADCs respectively codecs have nearly perfect anti-aliasing filters and decimation down to an intended sampling rate, partly even programmable.
