Beginner device CPLD/FPGA selection for anti-aliasing filter

Hi Dave, and many thanks for a quick answer!

With transformation I mean going from time to frequency domain to be able to perform harmonic analysis etc.

This could of course be done in the FPGA as well, but with current solution it is done later in a separate MCU.

Could you explain shortly what you mean by a single multiplier?

Unfortunately the filter you simulated seems to drop too much on frequencies below 3kHz.

I guess that creating a filter which passes signals <3kHz and blocks signals >3kHz is only

possible in theory, but something closer to that is required since I need to measure correctly up to the 50th harmonic (60Hz*50 = 3kHz...)

So how is that achieved? A higher order?

(As you notice, I am new to this...)

Best Regards

/ ShakeTheSpear