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Altera_Forum's avatar
Altera_Forum
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14 years ago

Ballpark Figure for Current Draw

I'm looking to pick some regulators for my board and for that I need to figure out how much current my Max V CPLD's consume.

I've used the Excel spreadsheet by Altera which helps in estimating the power draw. What struck me was how little it was and I'm a bit wary to trust it.

I have a 8MHz oscillator going into one of the global clock pins. In my design, the CPLDs are essentially 72 bit shift registers. As I understand, the IO power consumption depends upon the toggle rate of the IO pins. However, as I do not know what the data in the shift registers is going to be I do not know the toggle rate. So I assume a worst case of 100% i.e. the IO pins toggle at every clock cycle. Even when I choose this with a IO standard of LVTTL 16mA, the current draw is just 11.79mA.

Does this seem to correct? I understand that with such limited information it's hard to figure out the current draw but I'm just looking for a ball-park figure i.e. am I safe if I go with 1A? Do I need to jump further?

NOTE: Of course there are other devices on my board but I know their current draw. So I'm really just looking to see how much power my CPLDs consume.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Without looking into the details, 12 mA seems reasonable, because 8 MHz is really a low clock frequency for a device, that handles 100 and more MHz.

  • Altera_Forum's avatar
    Altera_Forum
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    For a correct I/O current calculation, don't forget to check that the capacitive loading is reasonable. If it is set to 0pF then it will be underestimated. That said the current seems reasonable. If the pins must drive a low impedance, you must also take that into account.

    Setting the IO standard to LVTTL 16mA doesn't mean that the component will always draw that much current, it is just the highest current sourced/sinked when changing the voltage level on the pin to charge/empty the load capacitance.