Altera_Forum
Honored Contributor
14 years agoBallpark Figure for Current Draw
I'm looking to pick some regulators for my board and for that I need to figure out how much current my Max V CPLD's consume.
I've used the Excel spreadsheet by Altera which helps in estimating the power draw. What struck me was how little it was and I'm a bit wary to trust it. I have a 8MHz oscillator going into one of the global clock pins. In my design, the CPLDs are essentially 72 bit shift registers. As I understand, the IO power consumption depends upon the toggle rate of the IO pins. However, as I do not know what the data in the shift registers is going to be I do not know the toggle rate. So I assume a worst case of 100% i.e. the IO pins toggle at every clock cycle. Even when I choose this with a IO standard of LVTTL 16mA, the current draw is just 11.79mA. Does this seem to correct? I understand that with such limited information it's hard to figure out the current draw but I'm just looking for a ball-park figure i.e. am I safe if I go with 1A? Do I need to jump further? NOTE: Of course there are other devices on my board but I know their current draw. So I'm really just looking to see how much power my CPLDs consume.