Average in VHDL..?

Hi,

in VHDL you can also either use the Megacore function or use the workaround as given in first post (which might internally be compiled rather identical).

The direct writing of a <= b/c will give an error as the compiler cannot resolve this to pure logic. Does this (in Verilog) really ends up with compiled code or is this syntax beind supported for simulation and/or testbench only (like Wait 500ms).