Avalon OpenCores Ethernet MAC and QII version 10 and higher

Hi all

Just to rev up the thread.

We are facing the same problem here. We have a design that uses ocm-eth and works using Q9.1sp2. It takes three hours to compile in 9.1 but only 25 mins in 10.1 or 11.1so we want to migrate to Q10 or Q11 :-)

It is a uClinux no-MMU system and ocm-eth seems to be working but there are no incoming or outgoing packets. Tx and Rx counters grow, there are no errors but no packets over the wire

Any news?

Thanks In Advance

Hi frd66 and keibee,

Could you eventually operate OpenCores mac with Qsys?

I'm now trying to migrate a design from 9.0sp2 (sopc builder) to 11.0sp1 with Qsys and I found this old thread.

The problem is similar to yours: all compiles fine, but I can't send/receive packets.

Actually my MAC transmit only the very first packet, but after this the dma seems to get stuck. I checked the descriptor control reg and I found it never becomes ready again until I reconfigure the fpga.

The control port works correctly: I can access mac registers and also the phy interface is ok. The problem seems to come from the rx/tx dma modules.

I applied the code patch Keibee posted, but I still can't receive anything.

Like you, I can never see rd/wr request signals switching on dma ports.

Hi Cris72,

Sorry, I stopped to use this core because there is no more support on it, and I suspect there is still a bug in it that makes the reception hang after a while (with the driver 'ethoc' under Linux/MMU).

I'm thus using the TSE in its full variation since QII v10.x, with better performances and less headache !

Thank you for answering, Fred.

Since I don't use Linux but I directly interface the core with my own driver, I hope I can overcome the problem... if I only could discover where it is!

Moreover, in my case it works perfectly with QII V9.0, so I think it's definitely a minor issue, something changed from SOPC to Qsys.

So far I could only discover this, by signaltapping the tx_dma module:

- 1st packet trasmission:

bd_read is pulsed, then pulse on valid_rdata, then pulse on stat_ready

ethernet frame correctly transmitted out

- 2st packet trasmission:

bd_read is pulsed, then pulse on valid_rdata, then rising edge on stat_ready;

at this point stat_ready is stuck to a high level until I reset everything

ethernet frame is not transmitted

I'll appreciate any comment or help