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Altera_Forum
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15 years ago

Avalon OpenCores Ethernet MAC and QII version 10 and higher

Hi, I'm migrating my design to QII 10.1sp1 (after an unsuccessful try with v11.0) and can observe a warning with SOPC builder about the parameter SYS_CLOCK_RATE:CLOCK_DOMAIN that must be of typ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi frd66 and keibee,

Could you eventually operate OpenCores mac with Qsys?

I'm now trying to migrate a design from 9.0sp2 (sopc builder) to 11.0sp1 with Qsys and I found this old thread.

The problem is similar to yours: all compiles fine, but I can't send/receive packets.

Actually my MAC transmit only the very first packet, but after this the dma seems to get stuck. I checked the descriptor control reg and I found it never becomes ready again until I reconfigure the fpga.

The control port works correctly: I can access mac registers and also the phy interface is ok. The problem seems to come from the rx/tx dma modules.

I applied the code patch Keibee posted, but I still can't receive anything.

Like you, I can never see rd/wr request signals switching on dma ports.