Avalon OpenCores Ethernet MAC and QII version 10 and higher

Thank you for answering, Fred.

Since I don't use Linux but I directly interface the core with my own driver, I hope I can overcome the problem... if I only could discover where it is!

Moreover, in my case it works perfectly with QII V9.0, so I think it's definitely a minor issue, something changed from SOPC to Qsys.

So far I could only discover this, by signaltapping the tx_dma module:

- 1st packet trasmission:

bd_read is pulsed, then pulse on valid_rdata, then pulse on stat_ready

ethernet frame correctly transmitted out

- 2st packet trasmission:

bd_read is pulsed, then pulse on valid_rdata, then rising edge on stat_ready;

at this point stat_ready is stuck to a high level until I reset everything

ethernet frame is not transmitted

I'll appreciate any comment or help