Avalon Memory Mapped pipelined slave writes

The naming is kinda confusing I agree. Maybe some background will explain it better. Long ago Avalon only supported posted writes. The term pipeline reads refers to the fact that reads can have a separate command and data phase meaning something is buffering the read commands (Qsys fabric and/or the slave). Writes on the other have concurrent command a data phase because the data goes out with the write command, I think that's what the spec is referring to as it not being pipelined. This is not to say the write command and data is not pipelined by the Qsys fabric or the slave being accessed.

With the addition of the write response signal now Avalon supports non-posted writes which allows your master to determine when the data is captured by the slave. Without the response it's not possible for a master to know when the write reached the slave but in both cases (posted and non-posted) there are typically at least 1 clock cycle between the write being send to the fabric and when the slave receives the write so the write data and command are typically pipelined through the fabric.

I haven't used pendingWriteTransactions but from that description you include the write response port for your slave and the value you specify tells Qsys how many 2-bit responses it should expect to need to buffer on the way back to a master. Masters do not have the ability to signal if they are doing a posted vs non-posted write so if you include the response port the responses will always be buffered (and will be tossed away if the master doesn't support the response input).