Altera_Forum
Honored Contributor
8 years agoAvalon interface verification problem
Hello good people, I have a test program which is simply some procedure to write data in avalon master bfm and will read it in an avalon slave bfm. The compilation is done without any error but in the simulation result it is not writing the data to avalon master bfm according to the test program. Can you please take a look and tell me what could be the problem here? Here I attach my relevant files.
Thanks in advance.