Avalon Interconnect Dynamic Bus Sizing and Bursts

Question

Hello!My Avalon-MM master has 32bit data width and is bursting capable.Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable.Will a 32bit read or write access to the slave cause the automatically generated Avalon adapter to translate the 1x32bit access to a single burst of 4 x 8bit?Or will there be 4 non bursting transfers of 8bit?My current testbench using Altera BFM shows a writeburstcount of 4, but when reading there is no readburstcount of 4.The bfm config output is following:# Loading work.test_program(test_program_arch)
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: - Hello from altera_avalon_mm_master_bfm
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   $Revision: #1 $
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   $Date: 2018/07/18 $
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_ADDRESS_W             = 12
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_SYMBOL_W              = 8
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_NUMSYMBOLS            = 4
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_BURSTCOUNT_W          = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   REGISTER_WAITREQUEST     = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_FIX_READ_LATENCY      = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_MAX_PENDING_READS     = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_MAX_PENDING_WRITES    = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READ                 = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WRITE                = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_ADDRESS              = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BYTE_ENABLE          = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BURSTCOUNT           = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READ_DATA            = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READ_DATA_VALID      = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WRITE_DATA           = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BEGIN_TRANSFER       = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BEGIN_BURST_TRANSFER = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WAIT_REQUEST         = 1
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_LOCK                 = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_DEBUGACCESS          = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_TRANSACTIONID        = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WRITERESPONSE        = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READRESPONSE         = 0
#                    0: INFO: tb.dut.master_0.mm_master_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_CLKEN                = 0
#                    0: INFO: ------------------------------------------------------------
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: - Hello from altera_avalon_mm_slave_bfm
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   $Revision: #1 $
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   $Date: 2018/07/18 $
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_ADDRESS_W             = 12
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_SYMBOL_W              = 8
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_NUMSYMBOLS            = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_BURSTCOUNT_W          = 4
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   REGISTER_WAITREQUEST     = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_FIX_READ_LATENCY      = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_MAX_PENDING_READS     = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_MAX_PENDING_WRITES    = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_READ_WAIT_TIME        = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   AV_WRITE_WAIT_TIME       = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READ                 = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WRITE                = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_ADDRESS              = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BYTE_ENABLE          = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BURSTCOUNT           = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READ_DATA            = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READ_DATA_VALID      = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WRITE_DATA           = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BEGIN_TRANSFER       = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_BEGIN_BURST_TRANSFER = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WAIT_REQUEST         = 1
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_LOCK                 = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_DEBUGACCESS          = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_TRANSACTIONID        = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_WRITERESPONSE        = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_READRESPONSE         = 0
#                    0: INFO: tb.dut.slave_0.mm_slave_vhdl_wrapper.&lt;protected&gt;.&lt;protected&gt;: -   USE_CLKEN                = 0
#                    0: INFO: ------------------------------------------------------------
# ** Note: Starting master test programThanks in Advance!

boont_intel · Answer

Hi Sir, Looks like this is duplicate of this thread:  https://forums.intel.com/s/feed/0D50P00004OOY1sSAH

binos · Answer

Yes, because it was in the wrong forum. Could you move/merge it, but because of the high inactivity in this forum i created a second thread before asking.

This thread has more information in it. I think the answer in the other thread is wrong / kept to simple.

boont_intel · Answer

Hi Sir,We are unable to merge it.I will suggest you to add the "more information" in the original thread. And please try to clarify and elaborate if you think the answer is inaccurate in the original post. Thanks for your understanding.

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Avalon Interconnect Dynamic Bus Sizing and Bursts

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