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Altera_Forum's avatar
Altera_Forum
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12 years ago

Avalon Bus Interface

Hello everybody;

How can I generate the waitrequest signal in my avalon slave logic, does it relat on the write or the address signals.

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You control when you want waitrequest is enabled. At a minimum, you should assert waitrequest when your slave is in reset.

    The signal exists to tell the Avalon MM Master to keep hold the current signals with the slave the same until waitrequest is deasserted. The two (signal level) exceptions are begintransfer and beginbursttransfer.

    There are plenty of examples out there. Have a look and you should be able to find what you want.

    Cheers!

    slacker
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanks Mr.slacker for your reply;

    I have a custom component that makes ciphering for the input data, I made this component as an avalon slave component, it has a pipelined structure with a fixed latency, I didn't know how to adapt the data-valid signal to wait for this latency, I try now to use a timer o generate this signal,is it true.

    thanks