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Altera_Forum
Honored Contributor
Honored ContributorAvalon Bus Interface
Hello everybody; How can I generate the waitrequest signal in my avalon slave logic, does it relat on the write or the address signals. Thanks
Altera_ForumHonored Contributor
Honored ContributorYou control when you want waitrequest is enabled. At a minimum, you should assert waitrequest when your slave is in reset.
The signal exists to tell the Avalon MM Master to keep hold the current signals with the slave the same until waitrequest is deasserted. The two (signal level) exceptions are begintransfer and beginbursttransfer. There are plenty of examples out there. Have a look and you should be able to find what you want. Cheers! slacker
