Altera_Forum
Honored Contributor
Honored ContributorAvalon Bus Interface
Hello everybody; How can I generate the waitrequest signal in my avalon slave logic, does it relat on the write or the address signals. Thanks
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Altera_ForumHonored Contributor
Honored ContributorThanks Mr.slacker for your reply;
I have a custom component that makes ciphering for the input data, I made this component as an avalon slave component, it has a pipelined structure with a fixed latency, I didn't know how to adapt the data-valid signal to wait for this latency, I try now to use a timer o generate this signal,is it true. thanks
