Honored ContributorHi.
I'm trying to build a system with address decoding in Qsys. What I want (see the picture) http://www.alteraforum.com/forum/attachment.php?attachmentid=9902&stc=1 - I want address BRAMs using one big address (with auto decoding). I can add an AXI bridge to Qsys with the same functionality, but AXI for that purpose is unnecessary. I can't find any Avalon bridge for that purpose. Do they exist? Can you help me please?
Honored ContributorYou don't need to create 4 separate BRAMs. Just use the on chip memory component wizard and give it the total size you need. QSYS isn't necessary if this is all you intend to put in it.
Honored ContributorI forgot to say - I show one master port at the picture (signals before decoder) but I need four master ports (so I need four decoders). So I can't use one big BRAM with one port.
Honored ContributorIf you are asking if there is a 4-port Avalon-MM bridge, the answer is no.
The best you can get is probably the MPFE Verilog. Or, you can do something like instantiate 4 bridges and connect them to the same slaves (onchip memories). You can then connect 4 masters to the bridges and then access to the memories will be arbitrated independently.Honored ContributorHonored ContributorQsys arbitration works on a per-slave basis. Any master can access any other slave while one slave is already busy.
(4) bridges (masters), each connected to the (4) onchip memories, can simultaneously access all of the onchip memories, so long a no two bridges are accessing the same slave at the same time. If you want to avoid conflict, avoid having your masters access the same memory at the same time (because they will briefly stall, waiting their turn).Honored ContributorThanks, ted.
I created a custom avalon bridge (avalon module with tied slave and master ports inside). I have four avalon bridges in the system. Main logic will control that no four bridges are accessing the same slave at the same time. You wrote "no two bridges are accessing the same slave at the same time". Do you mean "no four bridges", right?Honored ContributorIf one master is accessing one memory, then the second ( and any additional ) master to access that same memory will stall.
The stall first occurs with the second simultaneous access to the same memory, not the fourth.Honored Contributor
