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Altera_Forum
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11 years ago

Avalon bridge question

Hi. I'm trying to build a system with address decoding in Qsys. What I want (see the picture) http://www.alteraforum.com/forum/attachment.php?attachmentid=9902&stc=1 - I want address BRAMs usin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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If one master is accessing one memory, then the second ( and any additional ) master to access that same memory will stall.

The stall first occurs with the second simultaneous access to the same memory, not the fourth.

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OK, I see.