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Hi,
Thank you all for your quick response!
For conclusion: whether I run into timing problem or whether it's metastability problem, both of them should be dissipating if I'll use at least three synchronization register before I'll use the external data on my design. Am I right?
(Assuming, of course, that the design logic sustain it…)
Thanks,
Idan
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correct and more... we usually use two stage synchroniser but it depends how rich you are.
timing or metstability? these are linked but I prefer to say wrong sampling thus if you think of metastability you will think of statistics. But if signal transition hits the sampling window the flip will fail in one way or the other and wouldn't able to recognise the level which could be any.
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