Asynchronous Signal

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Hi.

I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divide [0-27], Pipe Line [20], Fmax=90MHz.

On ModelSim, the code works perfectly, but on Altera Evaluation Board (Cyclone IV)- the code stuck!. Using Altera SignalTap, I sew that my state machine is missing states and even jump to undefended state (completely disregard from the "when others =>Idan_State_Machine<=Idle_State;" line at the end of the state machine??!!).

When I transfered the external input signal to another register and then used it in my code- the problem seems to be disappearing.

How this is even possible? I agree that I should expect for one clock latency due to diss synchronization between the external input signal to the FPGA main clock, but to sent the state machine to the undefined state?! To stuke the code?

*Using two falling edge (idan_input_signal is the external input):

This is the partial code that failed:

" elsif clk'event and clk='1' then

idan_input_signal_buf <= idan_input_signal;

case Idan_State_Machine is

when Idle_State =>

if (Idan_input_signal_buf = '1' and idan_input_signal = '0') then "

This is the partial code that didn't failed:

" elsif clk'event and clk='1' then

Idan_input_signal_buf <= Idan_Input_Signal;

idan_input_signal_buf_two <= idan_input_signal_buf;

case Idan_State_Machine is

when Idle_State =>

if (Idan_input_signal_buf_two = '1' and Idan_input_signal_buf = '0') then "

Thanks,

Idan

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Reading your post again I feel it is very likely you run into timing problem. you are trying to detect change of signal (1 => 0).When input signal

is not registered you may get it anywhere including close to clock edge such that update does not occur in time and the change is therefore never detected as update occurs on next clock edge when both have changed by then.