When an asynchronous signal is fed into an FSM we have two pitfalls:
- difference in path delays: As the single input must propagate to all registers in the FSM it takes different paths and one (or more) registers see the change after the clock edge resulting in an undefined state.
- metastability: Even if all the changes are seen by the same clock edge some register input may fail to meet the required setup time and the register may transit in a metastable state, and the register may or may not reflect the intended change and you can end up with an undefined FSM state as well.
You can appreciate that the difference in path delays is dominant, because even if metastability did not exist (which it does) you still would end up with registers missing the intended value.
When you register the incoming asynchronous signal with a single register stage, the circuit will work (as long as the path delay + register setup times are smaller than the clock period, but TimeQuest will flag that error). But that single register synchroniser is now susceptible to metastability itself, in which case the output of the synchroniser register may take too long to settle bringing us back to the condition of different path delays upsetting the FSM. But don't hold your breath to see a single register synchroniser turn metastable: your circuit will work in the lab but fail at the customer.
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