Asynchronous Signal

iozana,

the frequency of failures due to meta-stability is statistical and will depend on the toggle rate of the signals, the hardware and the number of points of failure. It's not hard to get a design with MTBFs measured in seconds or less.

Considering that you have a design that works in real life but get's stuck on hardware, I wouldn't be so quick to dismiss meta-stability

There are multiple possibilities, some more mundane than others

a) This has nothing to do with meta-stability on asynchronous signals and you have just mis-constrained the synchronous parts of your design.

b) This is a meta-stability problem and you need to fix it.

c) You've got a jittery clock input. You need to fix that and/or account for it in the constraints, by adding clock uncertainty.

d) You've got power supply issues. You need to fix that.

e) You did everything right but TQ is missing a timing violation. You can try to over-constrain your design by adding (more) clock uncertainty to your constraints.

Regarding a, b, c and e, you should be able to reproduce the issue with a proper gate level simulation.

By default Quartus does not ignore the "others" clause, but it does optimize the SM logic by assuming the SM will never go into undefined states.

You can ask Quartus to generate more robust SM logic with the syn_encoding attribute.

VHDL: attribute syn_encoding of state_t : type is "safe";