--- Quote Start ---
Thanks for your replay!
Yes, in Quatus II I'm getting all good.
My colleague wrote the question on the same problem…
From my understanding, metastability is the statistic problem that should occur with time prior of years, so it don't make any sense that all the statistic had failed every time, after couple of seconds, with ~10 kHz external signal and 50MHz clock…
Is it possible?
If I'll extract from Quartus II timing the MTBF, will the result be several seconds? I don't think so.
I'f I'm right, I still don't have the answer to my wondering ("that I agree that I should expect for one clock latency due to diss synchronization between the external input signal to the FPGA main clock, but to sent the state machine to the undefined state?! To stuke the code?")
Idan
--- Quote End ---
Your thinking is right. We tend to exagerate metastability issue. In most cases what happens with asynchronous signals is that the logic is sampled wrong compared to simulation. For example in simulation you decide when your signals are driven but in actual hardware the drive may have different moments relative to clock and thus upsets the logic.
An asynchronous signal change will either hit timing window (and may cause metastability or not) or hit after timing window leading to delayed sample point.
Regarding undefined states: my understanding is that the tool ignores "when others" for state machine(but check that) and the advice is you better reset your state machine at start up rather than depend on "when others" and also make sure that your state transitions never enter undefined state.
Honored Contributor
