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Honored Contributor
Honored ContributorAsynch Design Challenge
After all the chat in this thread (http://www.alteraforum.com/forum/showthread.php?t=26151)regarding glitching in the outputs of asynchronous logic, I thought I would post the following challenge for people to discuss:
Design a circuit to divide a clock by 3, keeping a 1:1 mark to space ratio and to start working instantly with no delay. i.e. using a PLL isn't allowed. I will allow a reset pulse to get things going in simulation in a known state but a real implementation shouldn't need it. Extra bonus points for using the smallest amount of LEs. http://farm5.static.flickr.com/4131/5144985871_0171bb6cc5_z.jpg I'm rather proud of my solution which only uses three LEs (though it does have drawbacks). I'll post it in a couple of days so people can have a think about it first.12 Replies
Altera_ForumIt's a serial topic in electronic forums (and in job interviews, too). You can e.g. search edaboard.com for "divide by 3".
- Altera_Forum
I can do it with two sync reset DFFs, a toggle FF and a 2 input AND gate which I think should fit in 3 LEs.
The following pseudo code shows how I connect the above stuff.reg r1, r2, clkout: always @ (posedge clkin) begin if (reset) begin r1 <= 1'b0; r2 <= 1'b0; clkout <= 1'b0; end else if (r1 & r2) begin r1 <= 1'b0; r2 <= 1'b0; clkout <= ~clkout; end else begin r1 <= 1'b1; r2 <= r1; end end
