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Altera_Forum's avatar
Altera_Forum
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10 years ago

async fifo with variable length

Good day everyone!

I have async fifo with variable length in my FPGA project. Read and write clocks have the same frequency, but their phases are different and random. Also clocks are suffering some jitter and sometimes wander. I'm using right coding style (VHDL) for the buffer: write and read addresses are gray coded and synchronization reg are used (although I don't use timing assignments for sync registers so I'm not sure that compiler places them as close as possible to each other). The buffer is routing dependent (after some compilations it doesn't work properly). I can't use Altera dcfifo megafunction because buffer must have variable length. I would be grateful if someone gives me some advice about how to assign timing constraints for sync regs or how to make my buffer more sustainable.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    sync registers path is part of same clock domain and so are constrained based on clock speed. The issue here is to have best timing margin as well and I assume the tool recognizes sync chains. Otherwise you might try set max/min delay. This path must pass timing though physically it will get violated.

    The async path between write pointer and read pointer (or the reverse) is exempt from timing by clock grouping or false path. Here it is still best not to have them miles apart. so some people recommend set max delay but I am not sure if this constraint will survive clock grouping or set false path.