async fifo with variable length

sync registers path is part of same clock domain and so are constrained based on clock speed. The issue here is to have best timing margin as well and I assume the tool recognizes sync chains. Otherwise you might try set max/min delay. This path must pass timing though physically it will get violated.

The async path between write pointer and read pointer (or the reverse) is exempt from timing by clock grouping or false path. Here it is still best not to have them miles apart. so some people recommend set max delay but I am not sure if this constraint will survive clock grouping or set false path.