Altera_Forum
Honored Contributor
Honored ContributorAstronomer requesting Developemnt Feedback/Guidance (CycIII, Verilog)
Hi All,
First off: I'm an astronomer way out of my comfort zone! Second: I'm essentially asking for people to look at what I'm working on, talk about it with me, point out how I've screwed it up, and offer design advice and pointers. I'm not looking for someone to solve my problems (that said, if you are interested in freelancing, let's talk). I realize I've not asked any specific questions nor made any request beyond "Please read and share your thoughts". Admins, if there is a more suitable location for this post, please let me know or move it. I'm building a custom, high-speed imager for a structured light application in a new astronomical spectrograph. We've got a laser video projector, eight linear CMOS imager chips (Hamamatsu S10453), two 4 channel 8-bit ADCs (AD9289), a Cyclone III (EP3C40F324C8), and a Beagleboard xM (an ARM7 single-board-computer with high speed parallel interface for smartphone cameras and such). The general idea is that the FPGA is controlled via GPIO lines from the BBxM and horizontal (~25kHz, both edges used) and vertical synchronization (~60Hz) signals from the projector. It generates the clock and control signals needed by the imagers and ADCs, receives (and slightly processes) the data from the ADCs, and finally sends it to the BBxM via an 8-bit parallel camera interface. The analog front end is relatively simple: the FPGA provides a clock (10MHz) and a start signal to the imagers, when start is high they collect the light and when low they clock out the analog pixel data. The ADCs convert all 4 channels simultaneously on the clock, serialize each channel, and send the data out over 4 LVDS DDR channels along with a data clock and a frame clock (80, 40, and 10 MHz, respectively). The imager has a low-speed and a high-speed mode. In the low-speed mode we expose for an entire projected frame (1 projected frame = 1 4kB frame sent to BBxM). In the high-speed mode we expose for a single horizontal line, readout (roughly 2 lines time), then repeat, capturing lines 1,4,7,… of the first projected frame, dither in time by one horizontal line and capture lines 2,5,8… on the second frame, etc (5 projected frames = 1 ~2.4MB frame sent to BBxM). The logic behind these operating modes is complex and I won't get into it unless someone asks. I've made a first pass at a schematic top level with verilog modules (readme.rtf in archive). It compiles, but I've not done an SDC file yet, nor have I done logic simulation. I'm sure it would fail on both counts though. ;) I think this pretty much covers it. I'll keep working on the design. I'm about ready to start figuring out how to do my timing constraints and try doing functional logic simulations of some of the blocks. I don't really understand how to do either, but I've watched all the altera training videos and know that is basically my next step. I've attached the Quartus 12 project. Finally, I realize this is a large request and hope that this isn't violating the social conventions here. Anyway, regardless, thanks for reading. tl;dr: I'm an astronomer who just started working with FPGAs and verilog. I'm making a custom imager for a spectrograph destined for a observatory in Chile. I would appreciate help with development. Code is attached.
