Honored Contributor
Honored ContributorI realize you have provided an overview of the system, but it would be easier to comment on individual interfaces. Could you please draw a block diagram (or several block diagrams). Show the signals or buses going between devices (or question marks if you haven't figured it out yet).
Why use GPIO on the BeagleBoard xM, can't you just connect to the processor's local bus and have your FPGA memory mapped? I know you can do this with the BeagleBone, but I have not looked at the BeagleBoard, so cannot comment on that. Regarding the comments in the readme.rtf - I can help you figure out how to correctly synchronize your ADCs. Before you even start to worry about creating the synthesizeable code, you should be creating a Modelsim simulation of each piece of hardware you are interfacing to, and then write the Verilog to implement that interface. A model of each piece of hardware can usually be constructed by implementing its timing diagrams in Verilog. The model does not have to be a perfect copy of the real hardware, but it should reproduce the functions that you are using. Yeah, it sounds like twice as much code, but its not twice as much work, since you will save yourself debug time, and you are also forced to read the data sheet in detail, so you gain a better understanding of the devices. Cheers, Dave (radio astronomy)
