Assigning multiple LogicLock constraints to an instance

I think the best resources would be the Quartus Handbook. Here are a couple of links:

Volume 1, Chapter 13 http://www.altera.com/literature/hb/qts/qts_qii51017.pdf

Volume 2, Chapter 15 http://www.altera.com/literature/hb/qts/qts_qii52006.pdf

I found this in the Quartus Handbook, Volume 1, Chapter 13, page 50: "You can limit entity placement to a sub-area of a LogicLock region to create non-rectangular constraints. Construct a LogicLock hierarchy by creating child regions inside of parent regions, and then use the Reserved option to control which logic can be placed inside these child regions. Setting the Reserved option for the region prevents the Fitter from placing nodes that are not assigned to the region inside the boundary of the region." This will do what you want but I think it will exclude any other logic as well so depending on how many and how far apart the clusters are, it may be too limiting.

I'm not sure if it was just an example but for something like a memory controller, multiple tcl files and an SDC file are created when the controller is generated. They can be used to give Quartus what it needs during the fitter stage and report if it's failed to meet timing. I've found them to be quite helpful. Here's a link to documentation about those files: http://www.altera.com/literature/hb/external-memory/emi.pdf

In general, I find that the Quartus place and route algorithms are very good. In some of my past ISE designs, I've had to play a few tricks with location constraints to guide the fitter but the same designs ported to Quartus work well without such assignments. If timing is appropriately constrained using TimeQuest, I don't think you should have any problem.

Hope this helps.

After reading the documentation mentioned above, I found that there is a "merge" command in the Logic Lock command window. It allows creating custom-shaped regions, exactly what I was looking for.

Here is the qsf example "merge" command generates:

set_global_assignment -name LL_RECT X5_Y10 -width 10 -height 20 -section_id ag_2
set_global_assignment -name LL_RECT X25_Y10 -width 10 -height 20 -section_id ag_2

What is generated after FIT is a different story. But at least the QSF syntax now becomes clear to me.

I find that both Quartus and ISE place and route algorithms are inconsistent. And I cannot call either of them very good.

As an example, one design I have compiled with quartus 9.x has better timing results than compiled with 10.x. 11.x is a complete disaster. 12.x is better, but not as good as 9.x.

Designs I work with are challenging: multiple 250-300mhz clocks, 70-90% utilization, largest stratix 4 and 5 chips, high routing congestion. Build times are between 7 to 20 hours on powerful servers with lots of memory.

So the only solution is to do micro-floorplanning and fine-tuning of synthesis and p&r tool options. Yes, memory controller in my previous post is just an example. It's more complex than that.

Thanks,

Evgeni