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Regarding AS pins reuse, I think the only safe way is to keep one of the three input pins to the AS memory in an inactive state. Otherwise you can't exclude inadvertent corruption of the image. Also, the connected load must not bring on signal integrity issues for the AS communication.
Apart from this, indirect AS programming through works fine.
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If I understand the handbook correctly, when using DCLK; the FPGA only issues enough clocks to configure itself, and then disables the clock, correct? If so, then should resolve the issue of corruption. No clock = no writes or reads.
The user button could potentially cause errors - if it was pressed during indirect programming of the AS part. However, it seems like a simple enough solution - don't do that! That said, it may be a moot issue.
I just noticed the requirement on QFP parts regarding quiet pins around DCLK. Fortunately, one of the pins is DATA0, which I hadn't reused. Unfortunately, the other pin I had used as a low-side driver for an LED. It's not a critical component, so I can lose it. However, I may delete the user button, which could potentially cause glitches in programming, with the LED, instead. I can always implement a button on the user I/O port.
I wouldn't think an LED would alter the ASDO signal enough to corrupt data to the EPCS, would it? I would be sinking current through the LED - so it would light when the signal is driven low. I would think it would act a bit like a pull-up from the perspective of the EPCS. The caveat is that the LED is on the other side of the board. (about 2.5" away)
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