Honored Contributor
Honored ContributorI think the master templates that were posted to the altera wiki are probably the least complex. I'm not sure if they are highly tuned but the ones in the Qsys tutorial are very fast. All you would have to do is connect logic to them that tells them where to start reading/write, transfer length, and some control bits. This info is communicated via Avalon-ST which is a streaming protocol with a simple ready-valid handshake.
You can use whatever clock frequency you like. If the master is on a different clock domain than the memory controller slave port Qsys will insert clock crossing logic. My recommendation if you care about throughput to make sure the master is either on the same clock domain as the memory controller slave port or higher. Typically the memory slave port doesn't operate at a high frequency because by the time the data has been presented it has undergone a bunch of half rate conversions (half the clock, twice the width). So as long as you make the master wide enough you can saturate the memory bandwidth. That's the correct Uniphy doc, you can probably focus on the Qsys section since that's the flow applicable to your design.
