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Altera_Forum
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11 years ago

Arrow SOCkit DDR3 SDRAM controller?

Has anyone written a DDR3 SDRAM controller for the FPGA side of the SOCkit that they are willing to share? Or has anyone build a 'facade' type hardware component for the uniphy to allow it to be acce...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks. The video server reference design looks very helpful.

The path I'd tried was taking this and I ripped out the DMA stuff/connected it to the HPS axi master. https://github.com/zhemao/ddr3_dma_demo

Great to hear I don't need to use a full AXI master. The avalon MM interface is much simpler and if I can use that, with my choice of clock, to connect to uniphy that would be very helpful.

Do you mean these uniphy docs:uniphy design flow tutorials; external memory ... - altera (http://www.google.ch/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0cciqfjaa&url=http%3a%2f%2fwww.altera.com%2fliterature%2fhb%2fexternal-memory%2femi_tut_qdr.pdf&ei=yxvavjljj4kzpjt8gige&usg=afqjcnfhebp5elylq45yi-rkev__5tnwpq&sig2=vpe0osexki7ooviqimwygg&bvm=bv.83829542,d.zwu). Or is there a simpler version, that document is quite substantial/confusing to me!